VLSI program
Physical design
Place and connect the blocks of a digital design. Study how timing and power affect the layout.
Expert · mentor-led project
Plan the chip layout.
- Who it’s for
- Engineers ready to study chip layout, timing and power.
- What you’ll need
- RTL, synthesis and timing fundamentals.
- What you’ll build
- A chip layout study with documented timing and power trade-offs. This is a learning study; fabrication and tape-out are not included.
Inside this learning path
See what you’ll work on
An illustration of the concepts to discuss for your chosen project.
Give every block a place. And a path.
Plan the layout
Write, test and review your work
- Physical design flow
- Static timing analysis
- Low-power concepts
- Tape-out concepts
What you’ll build
Explore the curriculum A chip layout study with documented timing and power trade-offs. This is a learning study; fabrication and tape-out are not included.
The learning path
Curriculum overview
Apply the concepts through a project and review the decisions behind your work.
- Synthesis and implementation flow
- Floorplanning, placement and routing concepts
- Timing paths, constraints and STA
- Low-power design considerations
- Sign-off and tape-out concepts
Before you enroll
Fees & schedule
Ask us for the current fees, duration, weekly workload, dates and delivery arrangements for this program.
Is this the right path for you?
Share what you already know and what you want to work towards.