VLSI program
Design verification
Build a testbench, a simulation setup that checks a design. Use tests and waveforms to trace bugs.
Intermediate · mentor-led project
Check how a design behaves.
- Who it’s for
- Learners with basic RTL knowledge and engineers moving into verification.
- What you’ll need
- Digital logic and basic Verilog.
- What you’ll build
- A testbench, a verification plan and a record of the bugs you investigated.
Inside this learning path
See what you’ll work on
An illustration of the concepts to discuss for your chosen project.
One cycle can change the story.
Test the behavior
Write, test and review your work
- SystemVerilog
- UVM (Universal Verification Methodology) foundations
- Functional coverage
- Formal verification
What you’ll build
Explore the curriculum A testbench, a verification plan and a record of the bugs you investigated.
The learning path
Curriculum overview
Apply the concepts through a project and review the decisions behind your work.
- Verification planning and test strategy
- SystemVerilog testbench foundations
- UVM components and reusable environments
- Assertions, coverage and corner cases
- Formal concepts and failure analysis
Before you enroll
Fees & schedule
Ask us for the current fees, duration, weekly workload, dates and delivery arrangements for this program.
Is this the right path for you?
Share what you already know and what you want to work towards.